1. Field of the Invention
The invention relates to a frequency divider.
It can be applied, for example, to the field of frequency synthesis where the phase noise of the divider is a key performance characteristic.
In its general principle, a frequency divider with a division ratio N enables the output generation of a signal with a duration N*Te where Te is the period of the input signal of the divider. The output signal with a duration N*Te is generally constituted by only one high state and only one low state
When a divider is placed in a phase-locked loop, the static modification, in steps of one, of the N division ratio generates frequency steps at output of the loop. These steps are spaced out by the value of the comparison frequency of the loop. It is possible to generate frequency steps which are a fraction of this comparison frequency by using the divider in fractional mode. In this mode, after statically setting the N division ratio, this ratio is made to progress dynamically at the rhythm of the comparison frequency.
It is therefore worthwhile to design a divider with a capacity for the dynamic variation of its division ratio. This dynamic variation is generally achieved with values equal to some units. For example, the divider by N can vary dynamically by the five values N, N+1, N+2, N+3 and N+4, i.e. ΔN can take the values 0 to 4. Thus, for the phase-locked loop, an apparent division ratio Nmean is obtained. This apparent division ratio depends on the sequence of variation of N. For example, if the division is done alternately by N and N+1, then Nmean is equal to N+½.
The operation of the phase comparator of the phase-locked loop dictates duty cycle constraints for the signal coming from the divider.
Since the output signal from the divider has a high state and a low state, the following duty cycle constraints may be considered: for example, should one of the two states (high or low) of the output signal of the divider have a constant duration independent of ΔN, then:                When (Nmean) is an even-parity value, this constant duration is equal to Te*(Nmean)/2 where Te is the period of the input signal of the divider,        When (Nmean) is an odd-parity value, this duration is the value closest to Te*(Nmean)/2 where Te is the period of the input signal of the divider.        
2. Description of the Prior Art
FIG. 1 is a schematic view of the structure of a prior art frequency divider. It is formed by an input divider or prescaler 1 which divides the input frequency Fe by Na or by Na+1, a first counter 2 whose output TC commands the prescaler division by Na or Na+1, a second counter 3 whose output TC is the output of the device. Such a structure has especially the following drawbacks:                The counters 2 and 3 are synchronous counters for which all the stages must work at a high frequency equal to Fe/Na,        The implementation of the fractional modes is not easy,        The number of logic layers between the input and the output is generally great, thus restricting phase noise performance.        
The invention pertains to method and device of frequency division used especially to meet the need for dynamic variation of the N division ratio and for full control over the high and low states of the output signal of the divider.
The description makes use of the different definitions given here below.
The term “prescaler” is used to designate a divider that is placed at the front end of a division chain, generally has a simple structure and works at high speed.
The expressions “dynamic variation” or “static variation” of the division ratio are also defined below in the context of the present invention.
For any unspecified divider, two modes of variation of its division ratio may be envisaged.    1—In the dynamic variation mode, the passage from a division ratio N1 to a division ratio N2 is made without loss of continuity in the counting of the periods of the input signal Fe. FIG. 2 is a timing diagram showing the dynamic switching of a divider. Fe is the input frequency of the divider. The active edges of Fe are numbered in the figure. The edges 1, 4, 6 correspond to a start of the cycle of the divider: on these edges, the divider takes account of the value of the command which will determine the duration of the output cycle. An output cycle is counted between two rising edges of the output signal Fs. The diagram shows that the output cycles are joined together in perfect continuity without any lapse of time between them: this is what characterizes the dynamic switching of N.    2—When the output cycles of the divider are not joined in perfect continuity during the changes in division ratio, then the term “static switching” is used: the divider asks for a certain period of time to change its division ratio, and the changes in state that occur during this lapse of time are not always predictable.
In the description, the words “frames” and “cycles” designate two different notions explained here below.
For an N1 ratio divider, dynamically variable in response to the command C, the division of an input signal with a frequency Fe gives the output signal FS1. A counting cycle of the divider has a duration equal to N1 periods of Fe and is constituted by only one high state and only one low state. The counting frame of the divider designates a sequence of cycles FS1, and the duration N1*Te of each cycle is variable. The duration of this frame depends on the frame of the commands C. If the frame of the commands C is formed by X values, then the frame of FS1, has X cycles, each with a controlled duration.
A clear distinction must therefore be drawn between the frame of the commands of the divider and the counting frame: the command frame designates the sequence of the division values used to obtained the desired duration for the counting frame.
As shown in FIG. 3, the duration of the command frame may be different from the duration of the counting frame if the command is taken into account with a delay. In the timing diagram of FIG. 3, the period of the frames consists of two values. The passage from a command frame [2; 3] to a command frame [4; 2] is shown. A counting frame is obtained with a duration passing from 5Te to 6Te, but this is not the case of the command frame which goes from 5Te to 7Te and then to 6Te.